RISC-V International CEO Calista Redmond announced at Embedded World that there are now ten billion RISC-V cores on the market.

ARM RISC-V architecture shipped 10 billion cores, said to be more prominent than x86 and Arm architecture for the future

RISC-V, pronounced “risk five”, is an open standard instruction set architecture (ISA) provided under open source licenses that are free to use. The core instruction set has 32-bit fixed-length natively aligned instructions, and ISA supports variable-length extensions, meaning each instruction can be any numerical length within 16-bit blocks. The instruction set comes in 32-bit and 64-bit address space flavors and is designed for a wide range of uses. Various subsets support everything from small embedded systems to vector processor supercomputers and warehouse-scale rack-mounted parallel computers.

Calista Redmond said open standards are key.

Linux does it for software and we do it for hardware. We estimate there are 10 billion RISC-V cores on the market.

But the road to ten billion was not a fast one. It reportedly took seventeen years of trial and error for the ARM architecture to reach this milestone in 2008. RISC-V, on the other hand, only took twelve years to complete ten billion. Redmond predicts that the number of RISC-V processor cores will reach eighty billion by 2025.

Source: Embedded World 2022.

Included in the news was the announcement of four new specifications and an agreement to expand starting this year. The four new specifications they are:

  • The RISC-V specification for SBI establishes a software layer between the hardware platform and the operating system kernel using a binary interface of the application in controller mode (S-mode or VS-mode). This abstraction provides common platform services across all RISC-V operating system implementations. Many RISC-V members have already implemented the RISC-V SBI specification in their RISC-V solutions, so ratification of the specification will ensure compatibility by providing a standard approach throughout the RISC-V ecosystem. The development and ratification of this specification was led by Atish Patra of Rivos, with work carried out by the Platform’s Horizontal Steering Committee.
  • RISC-V UEFI Protocols bring existing UEFI standards to RISC-V platforms. The development and ratification of this specification was led by Sunil VL, Ventana Micro, and Philipp Tomsich, VRULL GmbH, and work was conducted in the Privileged Software Technical Working Group.
  • E-Trace for RISC-V defines a highly efficient approach to processor tracing using branch tracing, ideal for debugging any type of application, from small internal designs to super-powerful computers. For RISC-V documentation, E-Trace defines the signals between the RISC-V core and the encoder (or input port), the compressed branch trace algorithm, and the packet format to include the compressed branch trace information. The development and ratification of this specification was led by Picocom’s Gajinder Panesar and RISC-V’s E-Trace Task Force.
  • RISC-V Zmmul Multiply Only allows low-cost applications that require multiplication but not division and is part of the RISC-V Unprivileged Specification. The development and ratification of this extension was directed by Allen Baum, with work on the Non-Privileged ISA Committee.

News sources: IT House, RISV.org

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