New P and E Cores, Xe2-LPG Graphics, New NPU 4 Brings More AI Performance

This morning, Intel is lifting the lid on some finer architectural and technical details about its upcoming Lunar Lake SoC – the chip that will be the next generation of Core Ultra mobile processors. Once again hosting one of its increasingly regular Tech Tour events for media and analysts, Intel has set up shop in Taipei, this time ahead of the start of Computex 2024. During the Tech Tour, Intel revealed numerous aspects of Moon Lake, including the new P The basic design is the codename Lion’s Cove and a new wave of E-cores that bear some resemblance to Meteor Lake’s flagship Low Power Island E-Cores. Intel also announced the NPU 4, which Intel claims delivers up to 48 TOPS, surpassing Microsoft’s Copilot+ requirements for the new era of AI computing.

Intel’s Moon Lake represents a strategic evolution in mobile SoCs, building on last year’s Meteor Lake launch, with a focus on increasing power efficiency and optimizing performance across the entire platform. Lunar Lake dynamically allocates tasks to efficient cores (E-cores) or performance cores (P-cores) based on workload requirements using advanced scheduling mechanisms designed to ensure optimal energy usage and performance. Again, Intel Thread Director, along with Windows 11, plays a key role in this process, guiding the OS scheduler to make real-time adjustments that balance efficiency with computing power based on workload intensity.

Moon Lake: Designed by Intel, built by TSMC (and assembled by Intel)

While there are many aspects to Moon Lake, perhaps it’s best to start with the most striking: who built it.

Intel’s Moon Lake boards use none of its own foundries—a sharp departure from historical dominance and even the last Meteor Lake, where a compute board was made using the Intel 4 process. Instead, both slabs of split Moon Lake are made at TSMC using a mix of TSMC’s N3B and N6 processes. In 2021, Intel began to free up its chip design teams to use the best foundry, be it in-house or outsourced, and nowhere is that more evident than here.

Overall, Lunar Lake represents a second-generation split SoC architecture for the mobile market, replacing the Meteor Lake architecture in the low-end space. Currently, Intel has announced that it uses a 4P+4E (8-core) design, with hyper-threading/SMT disabled, so the total number of threads supported by the processor is simply the number of CPU cores, eg 4P+4E /8T.

The Lunar Lake build combines a synergistic collaboration between Intel’s architectural design team and TSMC’s manufacturing process nodes, bringing the latest Lion Cove P cores to Lunar Lake, which boosts Intel’s architectural IPC as you’d expect from the next generation. At the same time, Intel is also introducing Skymont E-cores, replacing Meteor Lake’s Low Power Island Cresmont E-cores. However, it’s worth noting that these E-cores are not connected to the ring bus like the P-cores, making them a kind of hybrid LP E-core and matching the efficiency of the more advanced TSMC N3B node in the double digits. gains in IPC compared to previous Crestmont cores.

The entire compute board, including P and E-cores, is built on TSMC’s N3B node, while the SoC die is made using TSMC’s N6 node.

On a higher level, Intel again uses Foveros packaging technology here. Both the compute and SoC (now “Platform Controller”) tiles sit on a mainboard, providing a high-speed/low-power route between the tiles and additional connectivity to and from the rest of the chip.

In another first for a mainstream Intel Core product, the Lunar Lake SoC platform includes up to 32GB of LPDDR5X memory on the chipset itself. It is organized as a pair of 64-bit memory chips offering a total of 128-bit memory interface. As with other vendors using bundled memory, this change means users won’t be able to upgrade just DRAM at will, and memory configurations for Lunar Lake will ultimately be determined by the SKUs Intel chooses to ship.

With Lunar Lake, Intel is also focusing heavily on artificial intelligence, as the architecture incorporates a new NPU called NPU 4. This NPU is rated for INT8 performance up to 48 TOPS, making it a Microsoft Copilot+ AI PC ready. This is the bar that all PC SoC vendors, including AMD and Qualcomm, are aiming for.

Intel’s integrated GPU will also be a contributing player here. While not a highly efficient machine like a dedicated NPU, the Arc Xe2-LPG brings with it dozens of additional T(FL)OPS of performance and some additional flexibility that an NPU lacks. So you’ll see that Intel will rate the performance of these chips in terms of total platform TOPS – in this case, 120 TOPS.

Intel’s collaboration with Microsoft further improves workload management through the legendary Intel Thread Director, optimized for applications such as the Copilot assistant. Given the timing of the Moon Lake launch, this sets the stage somewhat for Q3 2024, coinciding with the 2024 holiday market.

Intel Lunar Lake: Updating Intel Thread Director and Power Management Improvements

To say that energy efficiency is a major goal for Moon Lake would be an understatement. As Intel dominates the mobile PC CPU market (AMD’s share is still small), the company has been feeling pressure from Apple’s M-series customer-turned-rival Apple for the past few years. Silicon has been setting the bar for energy efficiency for the past few years. Now, as Qualcomm looks to do the same for the Windows ecosystem with its upcoming Snapdragon X chips, Intel is gearing up to make its own power play.

Intel’s power management updates for Thread Director and Lunar Lake show various and significant improvements over Meteor Lake. Thread Director uses a heterogeneous scheduling policy that initially assigns tasks to one E-core and expands to other E-cores or P-cores as needed. OS storage zones are designed to limit tasks to specific cores, which directly improves energy efficiency and provides the performance required by the right core for the workload at hand. Integration with power management systems and quad Power Management Controllers (PMCs) further enables the chip to make context-aware adjustments with Windows 11, ensuring optimal performance with minimal power consumption and waste.

Lunar Lake’s scheduling strategy effectively manages power-sensitive applications. One example Intel gave is that video conferencing tasks are stored in the core efficiency cluster and use E-cores to maintain performance while reducing power consumption by up to 35%, as shown in data provided by Intel. These improvements are achieved through collaboration with OS developers such as Microsoft for seamless integration to optimize the best balance between power consumption and performance.

Focusing on the power management system for Lunar Lake, Intel uses SoC power management that operates in efficiency, balance, and performance modes that are tailored and designed to match any workload requirements during operation. This multi-layered approach allows the Lunar Lake SoC to work efficiently. Again, like Intel Thread Director, PMCs can balance power usage with performance needs.

Intel plans to further improve Thread Director by increasing scenario granularity, implementing AI-based scheduling hints, and enabling cross-IP scheduling in Windows 11. These improvements essentially amount to workload management designed to improve overall energy efficiency and improve performance in a variety of applications. needed without wasting the energy budget by allocating lighter tasks to higher power P cores.

Over the next few pages, we’ll explore the new P and E cores and Intel’s integrated Arc Xe (Xe2-LPG) graphics update.